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External Memory Expansion Port (Port A)
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
BR
Type
Output
State During Reset,
Stop, or Wait
Reset: Output
(deasserted)
Signal Description
Bus Request —Asserted when the DSP requests bus mastership. BR is
deasserted when the DSP no longer needs the bus. BR is asserted or
deasserted independently of whether the DSP56311 is a bus master or a
State during Stop/Wait
depends on BCR[BRH]
bit setting:
? BRH = 0: Output,
deasserted
bus slave. Bus “parking” allows BR to be deasserted even though the
DSP56311 is the bus master. (See the description of bus “parking” in the BB
signal description.) The Bus Request Hold (BRH) bit in the BCR allows BR
to be asserted under software control even though the DSP does not need
the bus. BR is typically sent to an external bus arbitrator that controls t he
? BRH = 1: Maintains last priority, parking, and tenure of each master on the same external bus. BR is
state (that is, if asserted,
remains asserted)
affected only by DSP requests for the external bus, never for the internal
bus. During hardware reset, BR is deasserted and the arbitration is reset to
the bus slave state.
BG
Input
Ignored Input
Bus Grant —Asserted by an external bus arbitration circuit when the
DSP56311 becomes the next bus master. When BG is asserted, the
DSP56311 must wait until BB is deasserted before taking bus mastership.
When BG is deasserted, bus mastership is typically given up at the end of
the current bus cycle. This may occur in the middle of an instruction that
requires more than one external bus cycle for execution.
The default operation of this bit requires a setup and hold time as specified
in DSP56311 Technical Data (the data sheet). An alternate mode can be
invoked: set the asynchronous bus arbitration enable (ABE) bit (Bit 13) in
the OMR. When this bit is set, BG and BB are synchronized internally. This
eliminates the respective setup and hold time requirements but adds a
required delay between the deassertion of an initial BG input and the
assertion of a subsequent BG input.
BB
Input/
Output
Ignored Input
Bus Busy —Indicates that the bus is active. Only after BB is deasserted can
the pending bus master become the bus master (and then assert the signal
again). The bus master can keep BB asserted after ceasing bus activity
regardless of whether BR is asserted or deasserted. Called “bus parking,”
this allows the current bus master to reuse the bus without rearbitration until
another device requires the bus. BB is deasserted by an “active pull-up”
method (that is, BB is driven high and then released and held high by an
external pull-up resistor).
The default operation of this bit requires a setup and hold time as specified
in the DSP56311 Technical Data sheet. An alternate mode can be invoked:
set the ABE bit (Bit 13) in the OMR. When this bit is set, BG and BB are
synchronized internally. See BG for additional information.
BB requires an external pull-up resistor.
CAS
Output
Tri-stated
Column Address Strobe —When the DSP is the bus master, CAS is an
active-low output used by DRAM to strobe the column address. Otherwise,
if the Bus Mastership Enable (BME) bit in the DRAM control register is
cleared, the signal is tri-stated.
Note:
DRAM access is not supported above 100 MHz.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
2-7
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